High Data Rate DMT SERDES Design

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  • The research presented in this thesis involves implementing a high data rate wireline com- munications system using Discrete Multitone (DMT) transmission. A theoretical analysis of the model of channels typically used for serializer/deserializer SERDES chip to chip com- munication is done, showing the benefits of DMT through improved spectral efficiency, and simplified transceiver design due to the pseudo-narrowband characteristics of DMT. Sim- ulations results demonstrate this benefit by being able to achieve higher data rates than conventionally used non-return-to-zero (NRZ) and pulse-amplitude modulation (PAM) typ- ically used, even with typical channel correction circuitry such as continuous-time linear equalizers (CTLE) and decision-feedback equalizers (DFE). Furthermore, a combined bit- loading/power allocation and transmit side equalization algorithm is presented that can improve the data rate of the system and decrease its error rate. Measurement results are demonstrated using a digital-analog-converter (DAC) and analog-digital converter (ADC) test bed using realistic conditions for chip-to-chip communication with a data rate over 250 GB/s with sufficient overhead for forward-error-correction (FEC) coding needed to reduce the bit-error rate (BER).

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  • Copyright © 2022 the author(s). Theses may be used for non-commercial research, educational, or related academic purposes only. Such uses include personal study, research, scholarship, and teaching. Theses may only be shared by linking to Carleton University Institutional Repository and no part may be used without proper attribution to the author. No part may be used for commercial purposes directly or indirectly via a for-profit platform; no adaptation or derivative works are permitted without consent from the copyright owner.
Date Created
  • 2022


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