Domain-Specific Analog Accelerators for Artificial Intelligent Algorithms ImplementationPublic Deposited
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This thesis discusses some circuit designs for AI algorithm acceleration. Instead of using digital computing components for algorithm implementations, this thesis describes new ideas to design and implement algorithms directly at the circuit-level. The first large section is about feedforward algorithm implementations that include using 1*4 analog multiply-accumulation arrays for DSP algorithm implementation and 2*3*3 analog multiply-accumulation matrices for computer vision algorithm and artificial intelligent algorithm implementations. The second large section concerns backward algorithm implementations that include using programmable resistor-based feedback loop, 'Add-division circuit' for convolutional kernel training algorithm implementation, and 'Random matrix generator' for solving Diophantine equations of neural networks.
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- Copyright © 2022 the author(s). Theses may be used for non-commercial research, educational, or related academic purposes only. Such uses include personal study, research, scholarship, and teaching. Theses may only be shared by linking to Carleton University Institutional Repository and no part may be used without proper attribution to the author. No part may be used for commercial purposes directly or indirectly via a for-profit platform; no adaptation or derivative works are permitted without consent from the copyright owner.
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